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TJ2996 - DDR Termination Regulator

Description

Jul.

2010 - Rev.

Features

  • z z z z z z z z Source and sink current Low output voltage offset No external resistors required Linear topology Suspend to Ram (STR) functionality Low external component count Thermal Shutdown Available in SOP8, SOP8-PP Packages SOP8 / SOP8-PP PKG TJ2996.

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Datasheet Details

Part number TJ2996
Manufacturer HTC Korea
File Size 0.97 MB
Description DDR Termination Regulator
Datasheet download datasheet TJ2996 Datasheet
Additional preview pages of the TJ2996 datasheet.

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Full PDF Text Transcription

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DDR Termination Regulator FEATURES z z z z z z z z Source and sink current Low output voltage offset No external resistors required Linear topology Suspend to Ram (STR) functionality Low external component count Thermal Shutdown Available in SOP8, SOP8-PP Packages SOP8 / SOP8-PP PKG TJ2996 APPLICATION z DDR-I, DDR-II and DDR-Ⅲ Termination Voltage z SSTL-2 and SSTL-3 Termination z HSTL Termination ORDERING INFORMATION Device TJ2996D TJ2996DP Package SOP8 SOP8-PP DESCRIPSION The TJ2996 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.
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